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PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 zer ? -drift, high-voltage, programmable gain instrumentation amplifier check for samples: PGA280 1 features description 23 ? wide input range: 15.5v at 18v supply the PGA280 is a high-precision instrumentation amplifier with digitally-controllable gain and signal ? binary gain steps: 128v/v to 1/8v/v integrity test capability. this device offers low offset ? additional scaling factor: 1v/v and voltage, near-zero offset and gain drift, excellent 1 ? v/v linearity, and nearly no 1/f noise with superior ? low offset voltage: 3 v at g = 128 common-mode and supply rejection to support high-resolution precision measurement. the 36v ? near-zero long-term drift of offset supply capability and wide, high-impedance input voltage range comply with requirements for universal signal ? near-zero gain drift: 0.5ppm/ c measurement. ? excellent linearity: 1.5ppm special circuitry prevents inrush currents from ? excellent cmrr: 140db multiplexer (mux) switching. in addition, the input ? high input impedance switch matrix enables easy reconfiguration and system-level diagnostics ? overload conditions are ? very low 1/f noise indicated. ? differential signal output the configurable general-purpose input/output ? overload detection (gpio) offers several control and communication ? input configuration switch matrix features. the spi can be expanded to communicate ? wire break test current with more devices, supporting isolation with only four iso couplers. the PGA280 is available in a ? expandable spi ? with checksum tssop-24 package and is specified from ? 40 c to ? general-purpose i/o port +105 c. ? tssop-24 package related products applications features product ? high-precision signal instrumentation 23-bit resolution, analog-to-digital converter ads1259 ? multiplexed data acquisition chopper-stabilized instrumentation amplifier, ina333 rr i/o, 5v single-supply ? high-voltage analog input amplifier high-precision pga, g = 1, 10, 100, 1000 pga204 ? universal industrial analog input high-precision pga, jfet input, g = 1, 2, 4, 8 pga206 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 spi is a trademark of motorola. 3 all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2009, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. PGA280 gain network adc (ads1259) +5v +15v - 15v switch matrix and 100 a source sink and buffer m control register 7xgpio spi interface inp2 inn2 inp1 inn1 address mux spi PGA280
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package information (1) package package product package-lead designator marking PGA280 tssop-24 pw PGA280a (1) for the most current package and ordering information see the package option addendum at the end of this document, or see the ti web site at www.ti.com . absolute maximum ratings (1) over operating free-air temperature range, unless otherwise noted. PGA280 unit vsn to vsp 40 v supply voltage vson to vsop, and dgnd to dvdd 6 v signal input terminals, voltage (2) vsn ? 0.5 to vsp + 0.5 v signal input terminals, current (2) 10 ma output short-circuit (3) continuous operating temperature ? 55 to +140 c storage temperature ? 65 to +150 c junction temperature +150 c esd ratings human body model (hbm) 2000 v (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) terminals are diode-clamped to the power-supply (von and vop) rails. signals that can swing more than 0.5v beyond the supply rails must be current-limited. (3) short-circuit to vson or vsop, respectively, dgnd or dvdd. 2 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 electrical characteristics boldface limits apply over the specified temperature range, t a = ? 40 c to +105 c. at t a = +25 c, vsp = +15v, vsn = ? 15v, vson = 0v, vsop = 5v, dvdd = +3v, dgnd = 0v, r l = 2.5k ? to vsop/2 = vocm, g = 1v/v, using internal clock, buf inactive, v cm = 0v, and differential input and output, unless otherwise noted. PGA280 parameter conditions min typ max unit input offset voltage, rti (1) v os gain = 1v/v, 1.375v/v 50 250 v gain = 128v/v 3 15 v vs temperature (2) dv os /dt gain = 1v/v 0.2 0.6 v/ c gain = 128v/v 0.03 0.17 v/ c vsp ? vsn = 10 and 36v, vs power supply, rti psr 0.3 3 v/v gain = 1v/v, 128v/v vs external clock, rti (3) dv os /df 0.8mhz to 1.2mhz, gain = 1v/v 0.05 v/khz 0.8mhz to 1.2mhz, gain = 128v/v 0.001 v/khz long-term stability (4) gain=128 3.5 nv/month input impedance single-ended and differential > 1 g ? input capacitance, in1 / in2 single-ended 12 / 8 pf input voltage range gain = 1v/v, gain = 128v/v (vsn) + 2.5 (vsp) ? 2.5 v common-mode rejection, rti cmr gain = 1v/v 0.3 3 v/v gain = 128v/v 0.08 0.8 v/v over temperature gain = 128v/v 0.1 1.5 v/v single-ended output connection offset voltage, rti, se out v os gain = 1v/v, 1.375v/v, se 120 v gain = 128v/v, se 3 v vs temperature, se out dv os /dt gain = 1v/v, se 0.6 v/ c gain = 64v/v, se 0.05 v/ c input bias current (3) bias current i b gain = 1v/v 0.3 1 na gain = 128v/v 0.8 2 na over temperature i b gain = 1v/v, gain = 128v/v 0.6 2 na offset current i os gain = 1v/v, gain = 128v/v 0.1 0.5 na over temperature i os gain = 1v/v, gain = 128v/v 0.9 2 na noise voltage noise, rti; target e ni f = 0.01hz to 10hz r s = 0 ? , g = 128 420 nv pp f = 1khz r s = 0 ? , g = 128 22 nv/ hz f = 0.01hz to 10hz r s = 0 ? , g = 1 4.5 v pp f = 1khz r s = 0 ? , g = 1 240 nv/ hz current noise, rti i n f = 0.01hz to 10hz r s = 10m ? , g = 128 1.7 pa pp f = 1khz r s = 10m ? , g = 128 90 fa/ hz (1) rti: referred to input. (2) specified by design; not production tested. (3) see application information section and typical characteristic graphs. (4) 300-hour life test at +150 c demonstrated randomly distributed variation in the range of measurement limits. copyright ? 2009, texas instruments incorporated submit documentation feedback 3 product folder link(s): PGA280
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com electrical characteristics (continued) boldface limits apply over the specified temperature range, t a = ? 40 c to +105 c. at t a = +25 c, vsp = +15v, vsn = ? 15v, vson = 0v, vsop = 5v, dvdd = +3v, dgnd = 0v, r l = 2.5k ? to vsop/2 = vocm, g = 1v/v, using internal clock, buf inactive, v cm = 0v, and differential input and output, unless otherwise noted. PGA280 parameter conditions min typ max unit gain output swing: 4.5v (5) range of input gain ? to 128 v/v range of output gain: 1v/v and 1 ? 1 and 1 ? v/v gain error, all binary steps all gains 0.03 0.15 % vs temperature (6) (7) no load, all gains except g = 128v/v -0.5 2 ppm/ c no load, g = 128v/v -1 3 ppm/ c gain step matching (8) (gain to gain) no load, all gains see typical characteristics nonlinearity no load, all gains (9) 1.5 10 ppm over temperature (6) no load, all gains 3 ppm output voltage output swing from rail (8) vsop = 5v, load current 2ma 40 100 mv vsop = 2.7v, load current 1.5ma 100 mv capacitive load drive 500 pf short-circuit current i sc to vsop/2, gain = 1.375v/v 7 15 25 ma output resistance each output vop and von 200 m ? (vson) + (vsop) ? voltage range for vocm vsp ? 2v > vocm v 0.1 0.1 bias current into vocm i b 3 100 na vocm input resistance 1 g ? internal oscillator frequency of internal clock (6) (8) 0.8 1 1.2 mhz ext. oscillator frequency range 0.8 1 1.2 mhz frequency response gain bandwidth product (8) gbp g > 4 6 mhz slew rate (8) , 4v pp output step sr g = 1, c l = 100pf, buf on 1 v/ s g = 8, c l = 100pf 2 v/ s g = 128, c l = 100pf 1 v/ s settling time (8) t s 0.01% g = 8, v o = 8v pp step 20 s 0.001% g = 8, v o = 8v pp step 30 s 0.01% g = 128, v o = 8v pp step 40 s 0.001% g = 128, v o = 8v pp step 40 s overload recovery, input (8) 0.5v over supply, g = ? to 128 8 s overload recovery, output (8) 5.5v p input, g = 1v/v 6 s input multiplexer (two-channel) crosstalk, inp1 to inp2 at dc; gain = 128v/v < ? 130 db series-resistance (8) ? see figure 44 600 ? switch on-resistance (8) 450 ? current source and sink (8) to gnd 70 95 125 a input current buffer (buf) offset voltage (8) v os buffer active 15 mv (5) gains smaller than ? are measured with smaller output swing. (6) specified by design; not production tested. (7) see figure 10 for typical gain error drift of various gain settings. (8) see application information section and typical characteristic graphs. (9) only g = 1 is production tested. 4 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 electrical characteristics (continued) boldface limits apply over the specified temperature range, t a = ? 40 c to +105 c. at t a = +25 c, vsp = +15v, vsn = ? 15v, vson = 0v, vsop = 5v, dvdd = +3v, dgnd = 0v, r l = 2.5k ? to vsop/2 = vocm, g = 1v/v, using internal clock, buf inactive, v cm = 0v, and differential input and output, unless otherwise noted. PGA280 parameter conditions min typ max unit digital i/o supply: 2.7v to 5.5v input (logic low threshold) 0 (dvdd)x0.2 v input (logic high threshold) 0.8x(dvdd) dvdd v output (logic low) i out = 4ma, sink 0.7 v output (logic high) i out = 2ma, source dvdd ? 0.5 v sclk, frequency 10 mhz power supply: input stage (vsn ? vsp) specified voltage range 10 36 v operating voltage range 10 to 38 v quiescent current (vsp) i q 2.4 3 ma quiescent current (vsn) i q 2.1 3 ma power supply: output stage (vsop ? vson) specified voltage range vsp ? 1.5v vsop 2.7 5.5 v voltage range for vsop, upper limit (vsp ? 2v) > vocm, (vsp ? 5v) > vson (vsp) v (vsn) to voltage range for vson (vsp ? 2v) > vocm, vsp vsop v (vsp) ? 5 quiescent current i q vsop 0.75 1 ma power supply: digital (dvdd ? dgnd) specified voltage range 2.7 5.5 v voltage range for dvdd, upper limit (vsp) ? 1 v voltage range for dgnd, lower limit (vsn) v static condition, no external load, quiescent current (10) i q 0.07 0.13 ma dvdd = 3v temperature range specified range ? 40 +105 c operating range ? 55 +140 c thermal resistance ja ssop high-k board, jesd51 80 c/w (10) see application information section and typical characteristic graphs. copyright ? 2009, texas instruments incorporated submit documentation feedback 5 product folder link(s): PGA280
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com pin configuration tssop-24 dw package (top view) pin descriptions pin no. name description pin no. name description 1 von inverting signal output 13 dvdd digital supply 2 vop noninverting signal output 14 sdo spi slave data output 3 vocm input, output common-mode voltage 15 sdi spi slave data input 4 vsop positive supply for output 16 sclk spi clock input 5 vson negative supply for output, agnd 17 cs spi chip select input; active low 6 vsp positive high-voltage supply 18 gpio6 gpio 6, sync (in), osc (out), ecs6 7 inp2 aux input, noninverting 19 gpio5 gpio 5, bufa (out), ecs5 8 inn2 aux input, inverting 20 gpio4 gpio 4, buft (in), ecs4 9 inp1 signal input, noninverting 21 gpio3 gpio 3, ef (out), ecs3 10 inn1 signal input, inverting 22 gpio2 gpio 2, ecs2, mux2 11 vsn negative high-voltage supply 23 gpio1 gpio 1, ecs1, mux1 12 dgnd digital ground 24 gpio0 gpio 0, ecs0, mux0 6 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280 sclksdi sdo dvdd gpio0gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 cs inp1 inn1 vsn dgnd von vop vocm vsop vson vsp inp2 inn2 PGA280 16 15 14 13 24 2322 21 20 19 18 17 9 10 11 12 1 2 3 4 5 6 7 8
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 typical characteristics at t a = +25 c, vsp = +15v, vsn = ? 15v, vson = 0v, vsop = 5v, dvdd = +3v, dgnd = 0v, r l = 2.5k ? to vsop/2 = vocm, g = 1v/v, using internal clock, buf inactive, v cm = 0v, and differential input and output, unless otherwise noted. offset voltage production distribution (g = 128) offset voltage production distribution (g = 1) figure 1. figure 2. offset voltage drift distribution (g = 128) offset voltage drift distribution (g = 1) figure 3. figure 4. copyright ? 2009, texas instruments incorporated submit documentation feedback 7 product folder link(s): PGA280 - 20 - 18 - 16 - 14 - 12 - 10 - 8 - 6 - 4 - 2 0 2 4 6 8 10 12 14 16 18 20 offset voltage ( v) m 5045 40 35 30 25 20 15 10 50 population (%) - 1.0 - 0.9 - 0.8 - 0.7 - 0.6 - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 offset voltage drift ( v/ c) m 5045 40 35 30 25 20 15 10 50 population (%) - 300 - 270 - 240 - 210 - 180 - 150 - 120 - 90 - 60 - 30 0 3060 90 120150 180 210 240 270 300 offset voltage ( v) m 5045 40 35 30 25 20 15 10 50 population (%) - 0.20 - 0.18 - 0.16 - 0.14 - 0.12 - 0.10 - 0.08 - 0.06 - 0.04 - 0.02 0 0.02 0.04 0.06 0.10 0.12 0.14 0.16 0.18 0.20 offset voltage drift ( v/ c) m 5045 40 35 30 25 20 15 10 50 population (%)
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com typical characteristics (continued) at t a = +25 c, vsp = +15v, vsn = ? 15v, vson = 0v, vsop = 5v, dvdd = +3v, dgnd = 0v, r l = 2.5k ? to vsop/2 = vocm, g = 1v/v, using internal clock, buf inactive, v cm = 0v, and differential input and output, unless otherwise noted. common-mode rejection distribution (g = 128) common-mode rejection distribution (g = 1) figure 5. figure 6. gain error distribution (g = 128) gain error distribution (g = 1) figure 7. figure 8. 8 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280 - 0.20 - 0.18 - 0.16 - 0.14 - 0.12 - 0.10 - 0.08 - 0.06 - 0.04 - 0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 gain error (%) 7060 50 40 30 20 10 0 population (%) - 0.20 - 0.18 - 0.16 - 0.14 - 0.12 - 0.10 - 0.08 - 0.06 - 0.04 - 0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 gain error (%) 3025 20 15 10 50 population (%) - 3.0 - 2.7 - 2.4 - 2.1 - 1.8 - 1.5 - 1.2 - 0.9 - 0.6 - 0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 common-mode rejection ratio ( v/ ) m v 8070 60 50 40 30 20 10 0 population (%) - 3.0 - 2.7 - 2.4 - 2.1 - 1.8 - 1.5 - 1.2 - 0.9 - 0.6 - 0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 common-mode rejection ratio ( v/ ) m v 120100 8060 40 20 0 population (%)
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 typical characteristics (continued) at t a = +25 c, vsp = +15v, vsn = ? 15v, vson = 0v, vsop = 5v, dvdd = +3v, dgnd = 0v, r l = 2.5k ? to vsop/2 = vocm, g = 1v/v, using internal clock, buf inactive, v cm = 0v, and differential input and output, unless otherwise noted. gain error drift distribution vs gain error vs gain setting gain setting (mean with 3 ) figure 9. figure 10. maximum gain error deviation between gain error distribution vs sequential gain settings (mean with 3 ) gain setting (mean with 3 ) figure 11. figure 12. copyright ? 2009, texas instruments incorporated submit documentation feedback 9 product folder link(s): PGA280 1/8 1/4 1/2 1 2 4 8 16 32 64 128 3 8 1 gain setting (v/v) 0.150.10 0.05 0 0.050.10 0.15 -- - gain error (%) selected samples with typical performance 32 1 0 1 2 3 -- - gain error drift: mean 3 (ppm/ c) s 1/8 1/4 1/2 1 2 4 8 16 32 64 128 gain setting (v/v) 3 8 1 0.200.15 0.10 0.05 0 0.050.10 0.15 0.20 -- - - gain error: mean 3 (%) s 1/8 1/4 1/2 1 2 4 8 16 32 64 128 gain setting (v/v) 3 8 1 0.200.15 0.10 0.05 0 0.050.10 0.15 0.20 -- - - gain error: mean 3 (%) s 1/8 to 1/4 1/4 to 1/2 1/2 to 1 1 to 1 to 2 2 to 4 4 to 8 8 to 16 16 to 32 32 to 64 64 to 128 gain setting change 3 8 1
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com typical characteristics (continued) at t a = +25 c, vsp = +15v, vsn = ? 15v, vson = 0v, vsop = 5v, dvdd = +3v, dgnd = 0v, r l = 2.5k ? to vsop/2 = vocm, g = 1v/v, using internal clock, buf inactive, v cm = 0v, and differential input and output, unless otherwise noted. power-supply rejection vs frequency common-mode rejection vs frequency figure 13. figure 14. input-referred noise spectrum small-signal gain vs frequency figure 15. figure 16. input voltage range limits vs temperature bias current vs gain setting figure 17. figure 18. 10 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280 2.01.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 input bias current (na) 1 2 4 8 16 32 64 128 gain setting (v/v) 140120 100 8060 40 20 0 power-supply rejection ratio (db) 10 100 1k 10k 100k frequency (hz) vsn vsp 140120 100 8060 40 20 0 common-mode rejection ratio (db) 10 100 1k 10k 100k frequency (hz) 100 10 1 0.1 0.01 noise ( v/ ) m hz ? 0.1 1 10 100 1k 10k 100k frequency (hz) g = 1/8 g = 1 g = 4 g = 128 6050 40 30 20 10 0 1020 -- gain (db) 10 100 1k 10k 100k 1m 10m frequency (hz) 3.02.5 2.0 1.5 1.0 0.5 0 input voltage swing to rail (v) - 50 - 25 0 50 100 150 temperature ( c) ir - ir+ 25 75 125
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 typical characteristics (continued) at t a = +25 c, vsp = +15v, vsn = ? 15v, vson = 0v, vsop = 5v, dvdd = +3v, dgnd = 0v, r l = 2.5k ? to vsop/2 = vocm, g = 1v/v, using internal clock, buf inactive, v cm = 0v, and differential input and output, unless otherwise noted. input bias current distribution (g = 128) input bias current distribution (g = 1) figure 19. figure 20. input bias current and input offset current input offset current distribution (g = 1, g = 128) vs temperature figure 21. figure 22. copyright ? 2009, texas instruments incorporated submit documentation feedback 11 product folder link(s): PGA280 - 1.0 - 0.9 - 0.8 - 0.7 - 0.6 - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 bias current (na) 8070 60 50 40 30 20 10 0 population (%) - 1.0 - 0.9 - 0.8 - 0.7 - 0.6 - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 bias current (na) 9080 70 60 50 40 30 20 10 0 population (%) 10 86 4 2 0 2 4 6 8 10 -- - - - i /i current (na) bias os - 50 - 25 0 50 100 150 temperature ( c) in1_i _1 in1_i _128 in1_ _1 in1_i _128 bias bias offset i offset 25 75 125 i offset i bias - 1.0 - 0.9 - 0.8 - 0.7 - 0.6 - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 input offset current (na) 7060 50 40 30 20 10 0 population (%)
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com typical characteristics (continued) at t a = +25 c, vsp = +15v, vsn = ? 15v, vson = 0v, vsop = 5v, dvdd = +3v, dgnd = 0v, r l = 2.5k ? to vsop/2 = vocm, g = 1v/v, using internal clock, buf inactive, v cm = 0v, and differential input and output, unless otherwise noted. digital supply current quiescent current from supplies (vsp and vsop) with and without spi communication vs temperature vs temperature figure 23. figure 24. gain nonlinearity with end-point calibration (g = 1) gain nonlinearity vs temperature figure 25. figure 26. 12 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280 3.02.5 2.0 1.5 1.0 0.5 0 quiescent current (ma) i vsp q i vsop q - 50 - 25 0 50 100 150 temperature ( c) 25 75 125 - 50 - 25 0 50 100 150 temperature ( c) 25 75 125 9085 80 75 70 65 60 1.00.9 0.8 0.7 0.6 0.5 0.4 digital supply current, no spi ( a) m digital supply current, with spi (ma) i (no spi) dvdd i (with spi) dvdd 10 98 7 6 5 4 3 2 1 0 nonlinearity (ppm) - 50 - 25 0 50 100 150 temperature ( c) 25 75 125 01 2 3 4 5 6 7 8 9 10 -- - - - - - - - - nonlinearity (ppm) - 4 - 3 - 2 - 1 0 1 2 3 4 input/output voltage (v) selected samples with typical performance
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 typical characteristics (continued) at t a = +25 c, vsp = +15v, vsn = ? 15v, vson = 0v, vsop = 5v, dvdd = +3v, dgnd = 0v, r l = 2.5k ? to vsop/2 = vocm, g = 1v/v, using internal clock, buf inactive, v cm = 0v, and differential input and output, unless otherwise noted. positive output current limit distribution negative output current limit distribution figure 27. figure 28. output swing to rail vs temperature output current limit vs temperature (vsop ? vson = 5v) figure 29. figure 30. copyright ? 2009, texas instruments incorporated submit documentation feedback 13 product folder link(s): PGA280 2019 18 17 16 15 14 13 12 11 10 current limit (ma) positive negative - 50 - 25 0 50 100 150 temperature ( c) 25 75 125 100 9080 70 60 50 40 30 20 10 0 output swing to rail (mv) - 50 - 25 0 50 100 150 temperature ( c) 25 75 125 positive rail negative rail 8.08.8 9.6 10.4 11.2 12.0 12.8 13.6 14.4 15.2 16.0 16.8 17.6 18.4 19.2 20.0 20.8 21.6 22.4 23.2 24.0 positive current limit (ma) 1614 12 10 86 4 2 0 population (%) 8.0 8.8 9.6 10.4 11.2 12.0 12.8 13.6 14.4 15.2 16.0 16.8 17.6 18.4 19.2 20.0 20.8 21.6 22.4 23.2 24.0 negative current limit (ma) 1412 10 86 4 2 0 population (%)
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com typical characteristics (continued) at t a = +25 c, vsp = +15v, vsn = ? 15v, vson = 0v, vsop = 5v, dvdd = +3v, dgnd = 0v, r l = 2.5k ? to vsop/2 = vocm, g = 1v/v, using internal clock, buf inactive, v cm = 0v, and differential input and output, unless otherwise noted. switch-on resistance and series input resistance vs common-mode voltage at various supply switch-on resistance and series input resistance voltages vs temperature figure 31. figure 32. wire break current distribution wire break current magnitude vs temperature figure 33. figure 34. 14 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280 800700 600 500 400 300 200 100 0 resistance ( ) w switch on v = 15v s series in r - 50 - 25 0 50 100 150 temperature ( c) 25 75 125 - 20 - 15 - 10 - 5 0 5 10 15 20 common-mode voltage (v) 16001400 1200 1000 800600 400 200 0 resistance ( ) w series input resistance switch on at v = 18v s switch on at v = 15v s switch on at v = 10v s switch on at v = 5v s - 50 - 25 0 50 100 150 temperature ( c) 25 75 125 100 9896 94 92 90 88 86 84 82 80 wire break current ( a) m wire break negative wire break positive 75.0 77.5 80.0 82.5 85.0 87.5 90.0 92.5 95.0 97.5 100.0 102.5 105.0 107.5 110.0 112.5 115.0 117.5 120.0 122.5 125.0 wire break current ( a) m 4540 35 30 25 20 15 10 50 population (%) wire break +wire break -
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 typical characteristics (continued) at t a = +25 c, vsp = +15v, vsn = ? 15v, vson = 0v, vsop = 5v, dvdd = +3v, dgnd = 0v, r l = 2.5k ? to vsop/2 = vocm, g = 1v/v, using internal clock, buf inactive, v cm = 0v, and differential input and output, unless otherwise noted. influence of external clock frequency to influence of external clock frequency to vos performance (g = 128) vos performance (g = 1) figure 35. figure 36. step response (g = 128) step response (g = 8) figure 37. figure 38. step response (g = 1) output overload recovery figure 39. figure 40. copyright ? 2009, texas instruments incorporated submit documentation feedback 15 product folder link(s): PGA280 10 s/div m vop (1v/div) von (1v/div) inn1 (5v/div) ef_out err vson (gnd) g = 1, vsop (5v) - 0.20 - 0.18 - 0.16 - 0.14 - 0.12 - 0.10 - 0.08 - 0.06 - 0.04 - 0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 d m v ( v/khz) os 8070 60 50 40 30 20 10 0 population (%) - 0.20 - 0.18 - 0.16 - 0.14 - 0.12 - 0.10 - 0.08 - 0.06 - 0.04 - 0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 d m v ( v/khz) os 2520 15 10 50 population (%) 10 s/div m 5v/div 50mv/div 2v/div diff signal output (right scale) inn1 (left scale) error flag 10 s/div m 2v/div 500mv/div 2v/div diff signal output (right scale) inn1 single-ended (inp1 to gnd) (left scale) error flag 10 s/div m 5v/div 5v/div 2v/div diff signal output (right scale) inn1 (inp1 to gnd) (left scale) error flag (not latched)
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com typical characteristics (continued) at t a = +25 c, vsp = +15v, vsn = ? 15v, vson = 0v, vsop = 5v, dvdd = +3v, dgnd = 0v, r l = 2.5k ? to vsop/2 = vocm, g = 1v/v, using internal clock, buf inactive, v cm = 0v, and differential input and output, unless otherwise noted. oscillator frequency vs temperature input current buffer offset voltage distribution figure 41. figure 42. 16 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280 1.201.15 1.19 1.05 1.00 0.95 0.90 0.85 0.80 oscillator frequency (mhz) - 50 - 25 0 50 100 150 temperature ( c) 25 75 125 - 100 - 90 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 10 20 30 40 50 60 70 80 90 100 buffer offset voltage (mv) 3025 20 15 10 50 population (%)
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 application information description the PGA280 is a universal high-voltage instrumentation amplifier with digital gain control. it offers excellent dc precision and long-term stability using modern chopper technology with internal filters that minimize chopper-related noise. the input gain extends from ? v/v (attenuation) to 128v/v in binary steps. the output stage offers a gain multiplying factor of 1v/v and 1 ? v/v for optimal gain adjustment. the output stage connects to the low-voltage (5v or 3v) supply. figure 43 shows a block diagram of the device. figure 43. PGA280 block diagram a signal multiplexer provides two differential inputs. several signal switches allow signal diagnosis of wire break, input disconnect, single-ended (versus differential), and shorted inputs. the supply voltage of up to 18v offers a wide common-mode range with high input impedance; therefore, large common-mode noise signals and offsets can be suppressed. a pair of high-speed current buffers can be activated to avoid inrush currents during fast signal transients, such as those generated from switching the signal multiplexers. this feature minimizes discharge errors in passive signal input filters in front of the multiplexer. the fully differential signal output matches the inputs of modern high-resolution and high-accuracy analog-to-digital converters (adcs), including delta-sigma ( ) as well as successive-approximation response (sar) converters. the supply voltage for the output stage is normally connected together with the converter supply, thus preventing signal overloads from the high-voltage analog supply. internal error detection in the input and output stage provides individual information about the signal condition. integrating adcs may hide momentary overloads. together with the input switch matrix, extensive signal and error diagnosis is made possible. the serial peripheral interface (spi) provides write and read access to internal registers. these registers control gain, the current buffer, input switches, and the general-purpose input/output (gpio) or special function pins, as well as configuration and diagnostics. the gpio port controls the multiplexer (mux) and switches and indicates internal conditions; it can also be individually configured for output or input. a special cs mode for the gpio extends the communication to other external spi devices, such as data converters or shift registers. this special function is intended for spi communication via a minimum number of isolation couplers. additional proof for communication integrity is provided by an optional checksum byte following each communication block. copyright ? 2009, texas instruments incorporated submit documentation feedback 17 product folder link(s): PGA280 gain mux switch network, current source and sink, and buffer digital i/o vsp vsn vsop vson control registers dgnd dvdd inp1 inn1 inp2 inn2 spi 7x gpio vopvocm von
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com functional blocks both high-impedance input amplifiers are symmetrical, and have low noise and excellent dc precision. these amplifiers are connected to a resistor network and provide a gain range from 128v/v down to an attenuation of ? . the PGA280 architecture rejects common-mode offsets and noise over a wide bandwidth. the PGA280 features additional current buffers placed in front of the precision amplifier that can be activated on demand. when activated, these additional current buffers avoid problems that result from input current during dynamic overloads, such as the fast signal transient that follows the channel switching from a multiplexer. without the use of the additional current buffers, the fast signal transient would overload the precision amplifiers and high bias currents could flow into the protection clamp until the amplifiers recover from the overload. this momentary current can influence the signal source or passive filters in front of the multiplexer and generate long settling tails. activating this current buffer avoids such an overload current pulse. the buffer disconnects automatically after an adjustable time. for continuous signal measurement, the additional current buffers are not used. the switches in the input provide signal diagnostic capability and offer an auxiliary input channel (inp2 and inn2; see figure 44 ). both channels can be switched to diagnose or test conditions, such as a ground-referred, single-ended voltage measurement for either input. in this mode, each of the signal inputs can be observed to analyze common-mode offsets and noise. the primary input channel [inp1 and inn1] provides switches and current sources for a wire break test. a switch can short both inputs. it can also discharge a filter capacitor after a wire break test, for example. the signal inputs are diode-clamped to the supply rails. external resistors can be placed in series to the inputs to provide overvoltage protection. current into the input pins should be limited to 10ma. the output stage offers a fully-differential signal around the output reference pin, vocm. the vocm pin is a high-impedance input and expects an external voltage, typically close to midsupply. the 3v or 5v supply of the converter or amplifier, following the PGA280 outputs, is normally connected to vsop and vson; this configuration shares a common supply voltage and protects the circuit from overloads. the fully-differential signal avoids coupling of noise and errors from the supply and ground, and allows large signal swing without the risk of nonlinearities that arise when driving near the supply rails. the PGA280 signal path has several test points for critical overload conditions. the input amplifiers detect signal overvoltage and overload as a result of high gain. the output stage also detects clipping. these events are filtered with adjustable suppression delays and then stored for readout. a gpio pin can be dedicated for external indication either as an interrupt or in a monitor mode. a serial peripheral interface (spi) controls the gain setting and switches, as well as the operation modes and the gpio port pins. the spi allows read and write access to the internal registers. these registers contain conditions, flags, and settings, as described in the spi and register description section. they represent the gain setting for the input stage from 128v/v to the attenuation of ? v/v in binary steps and the output stage gain of 1v/v and 1.375v/v (1 ? ). the input mux and switches and the input buffers are also controlled by registers. internal error conditions are stored and may be masked to activate an external pin in the gpio port. this gpio port can be configured individually for either input or output or for a special function. in special function mode, the port indicates an error condition, generates cs signal, controls an external mux, and connects to the buffer control and oscillator. the port pin can act as a cs for an external spi device. this mode connects other spi devices [such as an analog-to-digital (a/d) converter] to the primary four-wire spi. this feature is especially desirable when using galvanically-isolated spi communication. an optional checksum byte further improves communications integrity. 18 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 input switch network figure 44 shows the arrangement of the input switches. they are controlled individually via the digital spi. the switches b1b, b2b, a1b, and a2b are controlled automatically with the buffer (buf) operation. figure 44. input switch diagram switches a and b select the signal input. input 1 (inp1 and inn1) provides two current sources and two switches that connect to vson (which is typically the analog ground). this configuration is intended for wire break diagnosis. d12 can discharge an external capacitor or generate a starting condition. switches c1 and c2 are used to measure the input voltage referred to gnd (vson); for example, with a1 and c2 closed. this scheme measures the voltage signal connected to the input pin (inp1) referred to a common ground. the buf output is protected against a short to vson. see the spi and register description section for more information about switch control. input amplifier, gain network and buffer the high-precision input amplifiers present very low dc error and drift as a result of a modern chopper technology with an embedded synchronous filter that removes virtually all chopping noise. this topology reduces flicker noise to a minimum and therefore enables the precise measurement of small dc-signals with high resolution, accuracy, and repeatability. the chopper frequency of 250khz is derived from an internal 1mhz clock. an external clock can also be connected, if desired. the gain network for the binary gain steps connects to the input amplifiers, thus providing the best possible signal-to-noise ratio (snr) and dc accuracy up to the highest gains. gain is controlled by register 0. this register can control the gain and address for an external mux in one byte. selectable gains (in v/v) are : 128, 64, 32, 16, 8, 4, 2, 1, ? , ? , and ? . the gain is set to 1/8v/v after device reset or power-on. copyright ? 2009, texas instruments incorporated submit documentation feedback 19 product folder link(s): PGA280 600 w 600 w vsp vson vson 100 a source m 100 a sink m f1 f2 d12 g1g2 c1 b1 a1b b1b a1 inp2 inp1 buf 600 w 600 w vson dvdd dgnd vson c2 b2 a2b b2b a2 inn2 inn1 buf vsn gain network serial peripheral interface and controls
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com programmable gain amplifiers such as the PGA280 use internal resistors to set the gain. consequently, quiescent current is increased by the current that passes through these resistors. the largest amplitude could increase the supply current by 0.4ma. in maximum overload, gain of 128v/v and each or the inputs connected to the opposite supply voltage, a current of approximately 27ma was measured. external resistors in series with the input pins that are normally present avoid this extreme condition. this current is only limited by the internal 600 ? and the switch-on resistance (see figure 44 ). current buffer designed for highest accuracy and low noise, both amplifier inputs are protected from dynamic overvoltages through clamps. the amplifier fast input slew rate (approximately 1v/ s) normally prevents these clamps from turning on, provided adequate signal filtering is placed before the input. however, the fast channel switching-transient of a multiplexer or switch is much steeper, and cannot be filtered; this type of transient generates a dynamic overload. the current buffers (buf) prevent this dynamic overload condition of the input. with the buffers not activated, figure 45 indicates the clamp current flowing as a result of a fast signal change. the ramp in the signal, measured at the input pins (inp1), is the resulting voltage drop across the 1.5k ? resistor. in the example measurement, this resistor is placed between the signal generator and the input pin of the PGA280. figure 45. buffer off: input clamp current flowing figure 46 shows a typical block diagram for multiplexed data acquisition. the transient from channel 1 to channel 2 , shown as a voltage step, dynamically overloads the amplifier. a current pulse results from the input protection clamp. without the activation of the buffers (see buf, figure 44 ), the clamp current charges the filter and the signal source. input low-pass filters are often set to settling times in the millisecond range; therefore, discharge currents from dynamic overload would produce long settling delays. 20 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280 1 s/div m signal input to inp1 ch 4, 2v/div 1.5k connecting to inp1 w ch 2, 2v/div diff signal output ch 1, 1v/div
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 note: current from the protection clamp into the signal source and filter produces a long settling delay. figure 46. typical block diagram for multiplexed data acquisition together with the switching command of the multiplexer or internal switching, the current buffers (buf) can be activated to prevent such clamp currents. the buffers do not have clamps as long as the signal remains within the supply boundaries. figure 47 shows an example of the input signal settling for both conditions: without and with the buffer activated. without the buffer, there is an obvious long settling, depending on signal and filter impedance. with the buffer activated, only the amplifier has to settle and no distorting current is reflected into the signal source and filter; no glitch is visible in this plot. the plot shows the resulting settling of the input signal for a positive and a negative signal step as indicated in figure 46 ; also shown are the spi signal and the bufa signal. figure 47. example for amplifier settling without (t 1 ) and with (t 2 ) buffer (buf) activated copyright ? 2009, texas instruments incorporated submit documentation feedback 21 product folder link(s): PGA280 instrumentation amplifier mux low-pass filters ch x ch 3 ch 2 ch 1 s1 s2 s3 s x ideal actual change of mux output voltage ch 1 ch 2 current into protection clamp long settling of voltage on ch 2 100 s/div m 5v/div 1v/div t 2 t 1 mux switching inputs to pga with buffer off inputs to pga with buffer on buffer activated
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com the buffers turn off automatically after a preset time (see register 3 , buftim). they are activated from bit 5 ('t') within the command byte. they can also be triggered by an external pin (buftin on gpio4). the bufa bit is active in conjunction with the buffer, indicating that the buffer is busy (see figure 55 ). error detection circuits observe the signal path for signal overvoltage (ioverr), amplifier output clipping (iarerr), and gain overload (gainerr). the input clamp activation indicator icaerr indicates that current was conducted into the dynamic clamp circuit. these indicators help prevent misinterpretation of the analog signal and diagnose critical input signal conditions, such as those that occur with integrating analog-to-digital converters that may hide momentary overloads and present inaccurate results. the buffers (buf) prevent current flowing from the signal source with a compromise of offset voltage. as soon as the buffers are turned off, the amplifiers settle back to high precision. for signal measurement without (multiplexer) switching transients, the buffer is not used. input protection the input terminals are protected with internal diodes connected to vsp and vsn. if the input signal voltage exceeds the power-supply voltage (vsp and vsn), the current should be limited to less than 10ma to protect the internal clamp diodes. this current-limiting can generally be accomplished with a series input resistor. emi susceptibility amplifiers vary in susceptibility to electromagnetic interference (emi), but good layout practices play a critical role. emi can generally be identified as a variation in offset voltage shifts. the PGA280 has been specifically designed to minimize susceptibility to emi by incorporating an internal low-pass filter. additional emi filters may be required next to the signal inputs of the system, as well as known good practices such as using short traces, low-pass filters, and damping resistors combined with parallel and shielded signal routing, depending on the end system requirements. output stage the output stage power is connected to the low-voltage supply (normally 3v or 5v) that is used by the subsequent signal path of the system. this design prevents overloading of the low-voltage signal path. the output signal is fully differential around a common-mode voltage (vocm). the vocm input pin is typically connected to midsupply voltage to offer the widest signal amplitude range. vocm is a high-impedance input that requires an external connection to a voltage within the supply boundaries. the usable voltage range for the vocm input is specified in the electrical characteristics and must be observed. the output stage can be set to a gain of 1v/v and 1 ? v/v. it is set to 1v/v after device reset or power-on, and is controlled by the gain multiplication factor. both signal outputs, vop and von, swing symmetrically around vocm. the signal is represented as the voltage between the two outputs and does not require an accurate vocm. therefore, the signal output does not include ground noise or grounding errors. noise or drift on vocm is normally rejected by the common-mode rejection capability of the subsequent signal stage. the signal that passes through the output stage is internally monitored for two error conditions: clipping of the signal to the supply rail and overcurrent. in fault conditions, an error flag bit is set (outerr). 22 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 output filter the PGA280 uses chopper technology for excellent dc stability over temperature and life of operation. it also avoids 1/f frequency (flicker) noise, and therefore enables both high resolution and high repeatability for dc measurements. while the chopper noise components are internally filtered, a minimal residual amount of high-frequency switching noise appears at the signal outputs. an external, passive, low-pass filter after the output stage is recommended to remove this switching noise; figure 48 shows two examples. this filter can also be used to isolate or decouple the charge switching pulses of an a/d converter input. figure 48. typical examples of recommended output filters single-ended output the output stage of PGA280 is designed for highest precision. the fully-differential output avoids grounding errors and noise, and delivers twice the signal amplitude compared to single-ended signals. however, if desired, the output can be taken single-ended from one of the output pins referred to the voltage at the vocm pin. the output stage errors now relate to half the signal amplitude and half the signal gain. the unused output is unconnected, but not disconnected from error detection. the usable voltage range for the vocm input is specified in the electrical characteristics and must be observed: the output swing (of both outputs) should not saturate to the supply. separate specifications for offset voltage and drift indicate higher offset voltage at lower gains, because some error sources are not cancelled in the output stage connected in single-ended mode. note that the gain is one-half of the gain set in reference to the gain table (see table 2 ). error detection the PGA280 is designed for high dc precision and universal use, but it also allows monitoring of signal integrity. the device contains an input switch network for signal tests and sense points that can indicate critical conditions. these added features support fully automated system setup and diagnostic capability. out-of linear range conditions are detected and stored in the error status register ( register 4 ) until reset. the input switches shown in figure 44 can be used to short the input to gnd, disconnect the signal, insert a 100 a test current, discharge external capacitance, and switch to a ground (vson)-referenced signal measurement to observe the signal at the pin (versus the differential measurement). figure 49 illustrates the diagnostic points available for error detection in the device architecture. all switches are controlled through the spi. the error signals can be combined using a logic or function to an output pin and eventually be used as an error interrupt signal. errors are normally latched, unless the ltd bit (latch disable) is set. the error sensors are filtered with a suppression delay ( register 11 ). these error signals are normally suppressed during the buffer (bufa) active time. copyright ? 2009, texas instruments incorporated submit documentation feedback 23 product folder link(s): PGA280 r 50 2 w r 50 1 w vop von r 100 4 w r 100 3 w vop von c 10nf 1 c 10nf 2 c 10nf 3
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com note: the signal path is observed for possible limitations; flags are stored and indicated in register 4 . figure 49. diagnostic points for error detection error indicators input clamp conduction (icaerr) the input clamp protects the precision input amplifier from large voltages between the inputs that occur from a fast signal slew rate in the input. this clamp circuit pulls current from the input pins while active. current flowing through the clamp can influence the signal source and cause long settling delays on passive signal filters. the current is limited by internal resistors of approximately 2.4k . dynamic overload can result from the difference signal as well as the common-mode signal. the input clamp turns on when the input signal slew rate is faster than the amplifier slew rate (see the electrical characteristics specification) and larger than 1v. appropriate input filtering avoids the activation. however, transients from mux switching, internal switches, and gain switching action cannot be filtered; therefore, to avoid these transients, it is recommended that the current buffer (buf) be activated. the buffer isolates the signal input from the clamp, and therefore avoids the current pulse (see figure 44 ). input overvoltage (ioverr) the input amplifier can only operate at high performance within a certain input voltage range to the supply rail. the ioverr flag indicates a loss of performance because of the input voltage or the amplifier output approaching the rail. gain network overload (gainerr) the gain setting network is protected against overcurrent conditions that arise because of an improper gain setting. the current into the resistors is proportional to the voltage between both inputs and the internal resistor; a low resistor value results in high gains. this error flag indicates such an overload condition that is the result of an improper gain setting. output amplifier (outerr) the output stage is monitored for signal clipping to the supply rail and for overcurrent conditions. 24 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280 a3 a1 a2 gain clamp clamp mux switch network, current source and sink, and buffer digital i/o error: input over-voltage error:input amp saturation error:output amplifier error:gain network overload vsp vsop vsn vson vsp vsn vsp vsn vsop vson error:clamp condition
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 checksum error (crcerr) spi communication can include a checksum byte for increased data integrity, when enabled. it is especially useful for an isolated spi. this error detection is only active with the checksum activated. see the checksum section for details. power supply the PGA280 can connect to three supply voltages: the high-voltage analog supply, the low-voltage output amplifier supply, and the digital i/o supply. this architecture allows an optimal interface (level-shift) to the different supply domains. the high-voltage analog supply, vsp and vsn, powers the high-voltage input section. the substrate of the ic is connected to vsn; therefore, it must be connected to the most negative potential. the low-voltage analog output supply, vsop and vson, can operate within the high-voltage supply boundaries with two minimal limitations: 1. the usable range for vson is from a minimum 5v below vsp to as low as vsn. this 5v provides the headroom for the output supply voltage of +2.7v to +5v. even with less than 5v supply, this voltage difference is required for proper operation. 2. the common-mode control input, vocm, requires a voltage at least 2v from vsp, in order to support internal rail-to-rail performance. these limits may only come into consideration when using a minimum supply or an extremely asymmetrical high-voltage supply. in most practical cases, vson is connected to the ground of the system 3v or 5v supply. vsop can be turned on first or can be higher than vsp without harm, but operation fails if vsp and vsn are not present. observe the maximum voltage applied between vsop and vson, because there is no internal protection. this consideration is the same as with other standard operational amplifier devices. the digital supply, dgnd and dvdd, can also be set within the boundaries of vsp and vsn. only the positive supply, dvdd, cannot be closer than 1v below vsp. it can be turned on without the analog supply being present and is operational, but limited to digital functions in this case. the maximum supply voltage must be observed because there is no internal protection. vsop and vson can be connected with dvdd and dgnd, if desired. current consumption of the digital supply is very low under static conditions, but increases with communications activity. assuming no external load except the 20pf load to sdo, with an sclk = 10mhz and a 3v supply, the current momentarily increases by approximately 0.6ma when reading a register (for example, reading register 14). with a 5v digital supply, the increase is in the range of 0.8ma. this additional current is only required during communication; a larger bypass capacitor can supply this current. driving current into sdo would further increase the current demand. vsn is connected to the substrate; therefore, the voltage at vson or dgnd must not turn on the substrate diode to vsn. use external schottky diodes from vson to vsn and from dgnd to vsn (refer to figure 50 ) to prevent such a condition. the PGA280 uses an internal chopper technology and therefore works best with good supply decoupling. series resistors in the supply are recommended to build an rc low-pass filter. with the small supply current, these series resistors can be in the range of 15 ? to 22 ? . the rc filter also prevents a very fast rise time of the supply voltage, thus avoiding parasitic currents in the ic. connecting supply wires into an already-turned on supply (very fast rise time) without such a filter can damage the ic as a result of voltage overshoot and parasitic charge currents. figure 50 shows an example of a supply connection using rc bypass filters. dvdd may not need decoupling, but if the digital supply is noisy, a filter is recommended at c 4 and r 4 . note rise and fall times for the high-voltage supplies must be slower than 1v/ s. copyright ? 2009, texas instruments incorporated submit documentation feedback 25 product folder link(s): PGA280
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com note: in this example, the schottky diodes prevent substrate reversing. the supply voltages shown are only example values. figure 50. supply connection example using rc bypass filters for good decoupling external clock synchronization the PGA280 uses an internal oscillator of 1mhz, nominally. this clock can be brought out to pin gpio6 if configured by the internal register setting to allow synchronization of external systems to this clock. if the PGA280 must be controlled by an external clock, gpio06 can be configured as an oscillator input, thus overriding the internal oscillator. the frequency range must be within the specified range shown in the electrical characteristics in order to maintain stable device performance. the clock pulse width is not critical, because it is internally divided down; however, less than 30% deviation is recommended. the gpio6 input assumes a standard logic signal. prevent overshoot at this pin, and provide approximately equal rise and fall time for the lowest influence on offset voltage as a result of coupled noise. expect a small amount of additional noise during the transition from internal to external clock, or vice-versa, for approximately eight clock periods because of phase mismatch. quiescent current the PGA280 uses internal resistor networks and switches to set the signal gain. consequently, the current through the resistor network may vary with the gain and signal amplitude. under normal operation, the gain-related current is low (less than 400 a). however, in signal overload conditions while a high gain is selected, this amount of current can increase. settling time the PGA280 provides very low drift and low noise, and therefore allows repeatable settling to a precise value with a negligible tail. signal-related load and power dissipation variables have minimal effect on the device accuracy. overload recovery overload conditions can vary widely, and there are multiple points in an instrumentation amplifier that can be overloaded. during input overload, the PGA280 folds the output signal partially back as a result of the differential signal structure and summing, but the error flags indicate such fault conditions. the amplifier recovers safely after removing the overload condition, as long as it is within the specified operating range as shown in figure 51 . avoid dynamic overload by using adequate signal filtering that reduces the input slew rate to the slew rate of the amplifier. fast signal jumps produced from multiplexed signal sources or gain changes cannot normally be filtered, but the current buffer (buf) stage can be activated to prevent current flowing through the input into the protection clamp in such situations. 26 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280 c 470nf 1 c 470nf 2 c 470nf 3 c 100nf 4 r 22 1 w r22 2 w r10 3 w r10 4 w +15v - 15v +5v +3v sd1 sd2 vsp vsn vson vsop dgnd dvdd PGA280 supply connections
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 figure 51. input clipping: negative side spi and register description the serial peripheral interface uses four wires: cs (input), clock (sclk, input), data in (sdi, or slave data input), and data out (sdo, or slave data output) and operates as a slave. cs is active low; data are sampled with the negative clock edge. it is insensitive to the starting condition of sclk polarity (spol = 1 or 0). see figure 52 and figure 53 . the spi communicates to the internal registers, starting with a byte for command and address. it is followed by a single data byte (exception: 11tx 0ccc requires no data byte). the communication can include a checksum byte. when enabled, this byte follows the last valid byte. either power on reset or software reset (sftwrrst) disables the checksum mode. writing to register 11 enables or disables checksum mode. on a read command, the device responds with the data byte and the checksum byte. if the checksum is not desired, setting cs to high terminates the transmission. multiple commands can be chained by holding cs low and sending the additional commands after the checksum byte (if checksum is disabled, send a dummy byte). in this mode, read and write instructions can be mixed. this interface allows clock rates up to 10mhz. such high clock rates require careful board layout, short wire lengths, and low parasitic capacitance and inductance. observe delays and distortion generated from isolation couplers. external drivers may be required to drive long and terminated cables. copyright ? 2009, texas instruments incorporated submit documentation feedback 27 product folder link(s): PGA280 inn1 clipped tovsn, ch 1, 5v/div vsnch 2, 5v/div output signalch 3, 2v/div overload error flag (ioverr), ch 4 2v/div 25 s/div m
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com command structure and register overview bit 7 is the most significant bit (msb); bit 0 is the least significant bit (lsb). binary numbers are denoted with 'b' . 'aaaa' is used to denote the encoded register pointer, 0000b to 1111b. 't' denotes the buffer trigger bit. writing to unassigned bits is ignored, but it is recommend to write a '0' for all unassigned bits. PGA280 registers, addresses, and functional information are summarized in the register map ( table 1 ). command byte 01t0 aaaa dddd dddd: write write 'dddd dddd' to internal PGA280 register at address aaaa 1000 aaaa 0000 0000: read read from specified internal PGA280 register at address aaaa [no buft on read]. the number of trailing zeros provides the clock for reading data. 16 sclk pulses are required when reading the data byte plus checksum. 00t0 aaaa: factory-reserved commands. 11t0 0ccc: direct cs command controls cs to pin (all pins are cs-capable, but not simultaneously; only one at a time) for ccc = 0 to 6, corresponding to gpio0 to gpio6, if cs mode is activated. within the command byte, t = 1 triggers the current buffer (buf). each command is terminated with setting cs to high; commands can be chained within a period of cs active low, but require a checksum byte, or a dummy byte when checksum mode is disabled. note buf cannot be triggered during a read command. here are several examples (discrete commands): read register 3: send 0x8300; response: 0xzz19 (this value is the initial setting of buftim). the first byte zz contains the line state (3-state) of sdo. the second byte is data. note the PGA280 sends the chksum, if clocks are available while cs: send 0x830000. response: 0xzz1937 write register 0: send 0x4018; set gain to 1v/v. write register 4: send 0x44ff; reset all error flags. read register 4: send 0x8400; response: 0xzz00 (no error flags set). 28 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 extended cs the PGA280 can generate an extended chip select ( ecs) for other devices that are connected to the same spi wires: sdo, sdi, and sclk. this ecs signal redirects the spi communication to the connected device, while the PGA280 ignores data and sclk. the cs signal to the PGA280 must stay low during such communication; as soon as cs returns high, spi communication is terminated. see the gpio operation mode section for details. table 1. register map (1) register (decimal, aaaa reset [hex]) (2) (binary) r/w b7 b6 b5 b4 b3 b2 b1 b0 description values (3) 0 0000 w/r g4 g3 g2 g1 g0 mux2 mux1 mux0 gain and optional mux register 0000 0000b sftwrrst 1 0001 w write-only register, soft reset, write 1 0000 0000b note2x 2 0010 w/r cp6 cp5 cp4 cp3 cp2 cp1 cp0 spi-mode selection to gpio-pin 0000 0000b buftim buftim buftim 3 0011 w/r buftim5 buftim3 buftim1 set buf time-out 0001 1001b 4 2 0 4 0100 w/r chkerr iarerr bufa icaerr ef outerr gainerr ioverr error register; reset error bit: write 1 0000 0000b gpio register data force out or 5 0101 w/r gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0000 0000b sense 6 0110 w/r sw-a1 sw-a2 sw-b1 sw-b2 sw-c1 sw-c2 sw-d12 input switch control 0110 0000b 7 0111 w/r sw-f1 sw-f2 sw-g1 sw-g2 input switch control 0000 0000b 8 1000 w/r dir6 dir5 dir4 dir3 dir2 dir1 dir0 configure pin to out = 1 or in = 0 0000 0000b 9 1001 w/r ecs6 ecs5 ecs4 ecs3 ecs2 ecs1 ecs0 extended cs mode (1 = enable) 0000 0000b mux-d iarerr bufapol icaerr ed bufa outerr gainerr ioverr 10 [a] 1010 w/r various configuration settings 0000 0000b dis dis at pin dis suppress dis dis dis flgtim flgtim chksu 11 [b] 1011 w/r ltd flgtim3 flgtim1 reserved various configuration settings 0001 0000b 2 0 me 12 [c] 1100 w/r oscout syncin bufaout buftin efout mux2 mux1 mux0 special function register 0000 0000b pin gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 register bit reference to gpio pin (4) (1) blank register bits are ignored and undefined. (2) registers 13 to 15 are for test purposes; read-only. (3) power-on reset values are sftwrrst values. (4) details for gpio pin assignments are shown in figure 54 . copyright ? 2009, texas instruments incorporated submit documentation feedback 29 product folder link(s): PGA280
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com spi timing diagrams (read and write) (sclk ? data ? cs) figure 52. write (to device) timing (gpx: command decoding); no checksum enabled. with checksum, command decoding occurs after 24th falling edge of sclk figure 53. read (from register) timing (gpx: command decoding); no checksum enabled. falling edge of sclk controls logic 30 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280 z z z d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 a3 a2 a1 a0 sdo sdi sclk cs gpx sampled here z z z do7 do6 do5 do4 do3 do2 do1 do0 x x x x x x x x cb7 b6 b5 b4 a3 a2 a1 a0 sdo sdi sclk cs gpx sampled here
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 gpio pin reference as shown in figure 54 , the PGA280 has seven multi-function pins labeled gpio0 through gpio6. these pins can function as general purpose input-output (gpio) pins either to read a digital input or to output a digital signal as an interrupt or control. gpio functions are controlled through register 5 and register 8 . these pins can also be programmed to have additional special functions for the PGA280. each of these seven pins can be used as an output for the extended chip select function ( ecs), using the PGA280 to redirect the spi communications to other connected devices. cs configuration mode is enabled through register 9. additionally, register 2 controls the clock polarity (cp) of each ecs. for each bit set to '1', a positive edge of sclk follows cs (cp = 0); for each bit set to '0', a negative edge of sclk follows cs (cp = 1). together with the gpio and ecs functions, the seven pins can perform more specialized input and output tasks as controlled by register 12 , the special functions register. gpio0, gpio1, and gpio2 can be used to control an external multiplexer. if the mux function is enabled in the first three bits of register 12, the output value on the mux pins is controlled through register 0. this configuration allows for simultaneous control of the PGA280 gain and external multiplexer settings by writing to a single register. gpio3 can be used to output an error flag. as with bit 3 of register 4, this option would be the logical or of the error bits in register 10 (iarerr, icaerr, outerr, gainerr, and ioverr). gpio4 can be used as an input to trigger the current buffer. the low-to-high edge of a pulse starts the buffer with a delay of three to four clock cycles. if held high, the buffer [bufa] remains active. it is extended by a minimum of three to four clock cycles in addition to the time set with flagtim. gpio5 can be configured as an output to indicate a buffer active condition. the polarity is controlled by bufapol of bit 5 in register 10. gpio6 can be configured as either an output or an input with the special functions register. with bit 7, oscout connects the internal oscillator to gpio6. with bit 6, syncin allows an external oscillator to provide the master clock to the PGA280. to use any of these functions, register 8 must first be set to '0' for input or to '1' for an output (for gpio, ecs, or special function). once set, any 1s in register 9 supersede the gpio function for the related pin, allowing for cs configuration. likewise, any 1s in register 12 supersede the gpio function and cs configuration, allowing for any of the pin-specific special functions to operate. figure 54. special function to pin assignment reference copyright ? 2009, texas instruments incorporated submit documentation feedback 31 product folder link(s): PGA280 gpio6gpio5 gpio4 gpio3 gpio2gpio1 gpio0 gpo/ecs6/oscout gpo/ecs5/bufout gpo/ecs4 gpo/ecs3/efout gpo/ecs2/mux2 gpo/ecs1/mux1 gpo/ecs0/mux0 gpi/syncingpi gpi/buftin gpi gpi gpi gpi
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com register information register details register 0: gain and external mux address (read = 0x8000; write with buf off = 0x40, write with buf on = 0x60) bit # d7 d6 d5 d4 d3 d2 d1 d0 bit name g4 g3 g2 g1 g0 mux2 mux1 mux0 por value 0 0 0 0 0 0 0 0 bit descriptions: g4: output stage gain setting. this setting is independent of the gain selected in the input stage and acts as a multiplication factor to the input gain. 0 = 1v/v output gain (power-on default) 1 = 1.375v/v output gain (= 1 ? v/v) g[3:0]: input stage gain setting. refer to table 2 . mux[2:0]: these ports can be used to control an external multiplexer. table 2. input stage gain settings g3 g2 g1 g0 gain 0 0 0 0 1/8 0 0 0 1 1/4 0 0 1 0 ? 0 0 1 1 1 0 1 0 0 2 0 1 0 1 4 0 1 1 0 8 0 1 1 1 16 1 0 0 0 32 1 0 0 1 64 1 0 1 0 128 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved 32 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 register 1: software reset register (write = 0x4101; write with checksum = 0x4101dd) bit # d7 d6 d5 d4 d3 d2 d1 d0 bit name ? ? ? ? ? ? ? sftwrrst por value 0 0 0 0 0 0 0 0 bit descriptions: sftwrrst: software reset. setting this bit to '1' generates a system reset that has the same effect as a power-on reset. all registers are reset to the respective default values; this bit self-clears. register 2: spi: mode selection to gpio-pin (read = 0x8200, write = 0x012) bit # d7 d6 d5 d4 d3 d2 d1 d0 bit name ? cp6 cp5 cp4 cp3 cp2 cp1 cp0 por value 0 0 0 0 0 0 0 0 bit descriptions: cp[6:0] spi mode1 or mode2 can be configured for each individual ecs (extended cs) output if activated in register 9. see cs mode in gpio operation mode for details. cp6 controls ecs6, for example. for spi mode1, set the respective bit to '1': a positive edge of sclk follows cs (clock polarity, cp = 0). for spi mode2, set the respective bit to '0': a negative edge of sclk follows cs (cp = 1). see also figure 56 . register 3: buf timeout register (read = 0x8300, write = 0x43) bit # d7 d6 d5 d4 d3 d2 d1 d0 bit name ? ? buftim5 buftim4 buftim3 buftim2 buftim1 buftim0 por value 0 0 0 1 1 0 0 1 bit descriptions: buftim[5:0] defines buf timeout length. the lsb equivalent is 4*t clk (nominal value is 4 s with a 1mhz clock). setting this register to 0x00 disables the buf. the minimum timeout length that can be set is approximately 6 s. the default/por setting sets bufa time on to 100 s. the bufa bit of the error register [d5] indicates the buffer active status. see figure 55 . register 4: error register (read = 0x8400, write = 0x44) bit # d7 d6 d5 d4 d3 d2 d1 d0 bit name chkerr iarerr bufa icaerr ef outerr gainerr ioverr por value 0 0 0 0 0 0 0 0 the error register flags activate whenever an error condition is detected. these flags are cleared when a '1' is written to the error bit. bit descriptions: chkerr: checksum error in spi. this bit is only active if checksum is enabled. this bit is set to '1' when the checksum byte is incorrect. iarerr: input amplifier saturation bufa: buffer active icaerr: input clamp active ef: error flag. logic or combination of error bits of register 10. this bit can be connected to gpio3 pin if it is configured for output (register 8) and as a special function (register 12). outerr: output stage error (allow approximately 6 s activation delay). gainerr: gain network overload ioerr: input overvoltage copyright ? 2009, texas instruments incorporated submit documentation feedback 33 product folder link(s): PGA280
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com register 5: gpio register (read = 0x8500, write = 0x45) bit # d7 d6 d5 d4 d3 d2 d1 d0 bit name ? gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 por value 0 0 0 0 0 0 0 0 bit descriptions: gpio[6:0]: the gpio bits correspond to gpio6 through gpio0, respectively. the function of each bit depends on whether the gpio pin is configured as an input pin or an output pin, which is determined by the setting in register 8. when the gpio pin is configured as an input, reading this register samples the gpio pin. when the gpio pin is configured as an output, reading from this register reads back the forced data. register 6: input switch control register 1 (read = 0x8600, write = 0x46) bit # d7 d6 d5 d4 d3 d2 d1 d0 bit name ? sw-a1 sw-a2 sw-b1 sw-b2 sw-c1 sw-c2 sw-d12 por value 0 1 1 0 0 0 0 0 bit descriptions: switch control; see figure 44 for switch designation (switch closed = 1). example: select inp2 and inn2: 0x18 // opens a1 and a2, and closes b1 and b2. register 7: input switch control register 2 (read = 0x8700, write = 0x47) bit # d7 d6 d5 d4 d3 d2 d1 d0 bit name ? ? ? ? sw-f1 sw-f2 sw-g1 sw-g2 por value 0 0 0 0 0 0 0 0 bit descriptions: switch control; see figure 44 for switch designation. register 8: gpio configuration register (read = 0x8800, write = 0x48) bit # d7 d6 d5 d4 d3 d2 d1 d0 bit name ? dir6 dir5 dir4 dir3 dir2 dir1 dir0 por value 0 0 0 0 0 0 0 0 bit descriptions: dir[6:0]: gpio configuration for input or output; 0 for input; 1 for output. power-on default is all inputs (requires external termination or set to output ). register 9: cs configuration mode register (read = 0x8900, write = 0x49) bit # d7 d6 d5 d4 d3 d2 d1 d0 bit name ? ecs6 ecs5 ecs4 ecs3 ecs2 ecs1 ecs0 por value 0 0 0 0 0 0 0 0 bit descriptions: ecs[6:0]: configure cs function to respective pins. see cs mode, in the gpio operation mode section (a single byte command applies). 34 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 register 10: configuration register 1 (read = 0x8a00, write = 0x4a) bit # d7 d6 d5 d4 d3 d2 d1 d0 bit name mux-d iarerr bufa pol icaerr ed bufa outerr gainerr ioverr por value 0 0 0 0 0 0 0 0 bit descriptions: mux-d: set this bit to '1' to disable mux control from register 0; set to '0' after reset. bufa pol: controls buf active indication polarity. set to '0' for high = active; set to '1' for low = active. ed bufa suppress: error detection is normally disabled during bufa active. errors are not suppressed if ed bufa = 1. error flags are logic or-combined and connected to the ? efout ? in register 12 as well as connected to the gpio3 output pin if configured. the efout signal is active high. assigned errors can be disabled individually using this or function, with the exception of ? chkerr ? , by writing a '1' to the error bit position. [iarerr; icaerr; outerr; gainerr; ioverr] register 11: configuration register 2 (read = 0x8b00, write = 0x4b) bit # d7 d6 d5 d4 d3 d2 d1 d0 bit name ltd ? flgtim3 flgtim2 flgtim1 flgtim0 reserved chksume por value 0 0 0 1 0 0 0 0 bit descriptions: ltd: individual error signals are not latched if this bit is set to '1'. with efout activated on gpio3, the error condition can be observed in real time, but error suppression time is applied. clear errors in register 4 after writing '1' to this bit. flagtim0 to 3: choose the number of clock cycles (nominally 1mhz) according to table 3 for suppression of the error flags in register 4. the timeout starts after the end of bufa. alternatively, it can start with the event if the buffer is not active or register 10, bit 3 is set high. allow delayed activation for the individual error sources in the microsecond range. table 3. error flag suppression time flgtim [3:0] clock cycles (1) 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 12 1010 16 1011 24 1100 32 1101 48 1110 64 1111 127 (1) clock cycles refer to internal clock or syncin; nominally 1mhz. copyright ? 2009, texas instruments incorporated submit documentation feedback 35 product folder link(s): PGA280
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com chksum is enabled by writing a '1' to this bit. a correct checksum is always required for enabling. once set, all communication to the device requires a valid checksum, until '0' is written to this bit. alternatively, a software reset [0x4101dd] or power-on reset can be performed to reset this function. register 12: special functions register (read = 0x8c00, write = 0x4c) bit # d7 d6 d5 d4 d3 d2 d1 d0 bit name oscout syncin bufaout buftin efout mux2 mux1 mux0 por value 0 0 0 0 0 0 0 0 bit descriptions: special function pin designation: set to '1' for activation. oscout: internal oscillator connected to pin gpio6 for output (gpio6 configured as an output). syncin: external connection for external oscillator input to pin gpio6 (gpio6 configured as an input). bufaout: pin gpio5 indicates a buffer active condition (if configured as an output). the bufa output signal is active high by default, but can be inverted to active low by bufa pol. buftin: the current buffer can be triggered externally by pin gpio4, if configured as an input. the low-to-high edge of a pulse starts the buffer with a delay of three to four clock cycles. if held high, the buffer [bufa] remains active. it is extended by a minimum of three to four clock cycles plus the time set with flagtim. efout: a logic or combination of error bits; see register 10 . this flag can control gpio3 if this pin is configured as an output and efout = 1. mux2 to mux0: if the gpio pins are configured as outputs and these bits are set to '1', the gpio pins are controlled from register 0 (if mux-d = 0). gpio configuration register priority: if gpio pins are used, follow this procedure: first, configure individual i/o bits as either inputs or outputs (register 8); '0' = input, '1' = output. bits b0 to b6 are connected to gpio0 to gpio6, respectively. then, configure individual bits to the desired function. when configuring for output, set the data register (register 5) first to avoid glitches. to configure the gpio pins for the cs function (see register 9 ): ? configure ecs ('0' = disable, '1' = enable). if set to '1' and the i/o configuration is set to output as well, this pin becomes ecs. details of this configuration are described in gpio operation mode , cs mode . ? configure for clock polarity (cp), relative to ecs in register 2; see register 9 . set this bit to '0': a negative edge of sclk follows ecs (cp = 1). set this bit to '1': a positive edge of sclk follows ecs (cp = 0). ? configure for special function (register 12): special function signals can be assigned to the gpio pins in this manner: 0 = disable, 1 = enable. pins xxout must be configured as outputs, and xxin must be configured as inputs in register 8. ? gpio data to force (register 5) gpio data (1 = low, 0 = high). forcing a bit, which is assigned to a special function, may be stored until gpio is enabled. note data may be stored in internal registers and therefore may show on a given gpio pin after the configuration is changed. 36 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 buffer timing the buffer is used to isolate fast transients from the overload protection of the high-precision amplifier. it avoids current into the overload clamp. fast transients result from the switching transient of a signal multiplexer or a gain change; these transients cannot be filtered in the signal path. the buffer can be turned on by software using the 't' bit in the spi command or by activating a gpio pin. the on-time of the buffer is set in register 3 (buftim). if controlled by software command, the buffer turns active (indicated by bufa shown in figure 55 ) with the last falling edge of sclk. controlling an external mux through register 0 activates the gpio pins after the rising edge of cs, providing an extra delay. alternatively, the buffer can be controlled by gpio4, after configuration (register 8, bit 4 = 0, and 0x4c10). a rising edge triggers the buffer with a delay of three to four clock cycles. if held high, the buffer [bufa] remains active. it is extended by a minimum of three to four clock cycles plus flagtim. the buffer active condition can be observed at gpio5, after configuration for output and special function (0x4820, 0x4c20). the time reference is the end of cs. the buffer is turned on with the 16th falling edge of the sclk and writing to register 0 (0x6018). bufa stays high for 6 s (buftim0) after cs. figure 55. bufa timing gpio operation mode the six gpio port pins can be configured individually in several modes: as inputs or outputs; a special cs mode; and a connection to the PGA280 internal special function register that contains control signals or indications. see table 1 for details. the gpio can be accessed through spi as soon as supply voltage is connected to dvdd and dgnd. input: standard cmos high-impedance input, no internal termination. terminate externally if not used or set to output. note: the gpios are all set as inputs after a device reset. output: push-pull output. output current is derived from dvdd and from dgnd. avoid i/o activity and high current during high-precision measurements to avoid coupled noise. special function i/o: the configuration allows connecting a designated pin to the special function register (register 12): oscout, syncin, bufaout, buftin, efout, mux2, mux1, and mux0. the pin must be configured as an input or output according to the pin function. example (chksum not enabled): 0x480b gpio0, gpio1. and gpio3 set to output 0x4c0b gpio0 and gpio1 connected to mux0 and mux1, efout connected to gpio3. mux0 and mux1 are controlled from register 0. copyright ? 2009, texas instruments incorporated submit documentation feedback 37 product folder link(s): PGA280 bufa sdi sclk cs 2.5 s/div m 5v/div
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com cs mode a special cs mode for the gpio extends the device communications to other external spi devices, such as data converters or shift registers. this cs function is intended for spi communication using four isolation couplers. to use this mode, follow this procedure: configure the desired gpio pins as outputs in register 8, then configure the respective ecs (extended cs) bits in register 9. register 2 allows control of the clock mode by cpn ( n for the individual ecs pins). cp = 1 asserts ecs after the last negative sclk edge of the command; cp = 0 asserts ecs after the positive sclk, as figure 56 shows. use the cs command 1100 0cccb [ccc = cs coded for 0 to 7] to activate ecs on a single gpio pin. example for ecs on pin gpio1 (chksum disabled): 0x4802 gpio1 configured output ( note: gpio may output a previously stored state; default is all zeroes) 0x4902 assign cs ( ecs) mode to gpio1 0xc1 single byte command to activate cs on gpio1 (1) cpn = 0; the red edge applies if cpn = 1. figure 56. timing for gpio pin acting as cs ( ecs) to external device this cs pin ( ecs) stays low as long as cs to the PGA280 is held low. the PGA280 sdo is turned to a high-impedance output (and requires external termination). the PGA280 ignores both clock and data signals during this time. therefore, data can be read and written to another device selected by the ecs port. communication is terminated by setting cs (to the PGA280) to high; this toggle also sets the port ecs to high and terminates the i/o transfer with the other device. figure 56 shows the timing for the gpio-generated ecs pulse in clock mode spol = 1 (sclk is high after cs asserts low). register 2 allows activating spol = 0 by writing a '1' to the cp bit, according to spi mode1. the initial setting is spol = 1. mode1; set bit to '1': a positive edge of sclk follows after ecs asserts low (cp = 0). see the red edge of the gpio trace in figure 56 . mode2; set bit to '0': a negative edge of sclk follows after ecs asserts high (cp = 1). see the black edge of the gpio trace in figure 56 . the negative edge of sclk senses data. the positive edge of sclk sets data on the data out line (if applicable). for spi modes 0 or 3, sclk must be inverted to indirectly sense data with the positive edge of sclk. figure 57 shows an example of connecting additional spi devices, addressed by the ecs. the or connection for sdo can be a wired-or if all devices provide a 3-state output option with the respective device cs ( ecs) set high. the spi interface allows clock rates higher than 10mhz. clock rates less than10mhz are recommended when using the ecs mode for less critical printed circuit board (pcb) layout and timing. observe delays and distortion generated from isolation couplers. external drivers may be required to drive long and terminated cables. 38 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280 cs to PGA280 cs sclk sdi sdo gpio PGA280 3-state cpol = 1 0xc1 data to external device ecs (1)
PGA280 www.ti.com ................................................................................................................................................ sbos487a ? june 2009 ? revised september 2009 with only four isolation couplers (digital galvanic isolation) connected in the spi wires, the spi can provide galvanic isolation for input and output channels. figure 57 shows a block diagram of how to connect spi devices selected by the ecs (extended cs) signal. isolation couples or long spi cables in harsh industrial environment are sensitive to impairments. for improved communication integrity, the communication can be extended with a checksum byte. figure 57 shows an example of the gpio pins used for both the extended chip select and special functions. the chip select ( cs) is connected to the PGA280 alone. the serial data input (sdi) and the serial clock (sclk) are shared connections, and are connected to all devices [PGA280, a/d converter, and the shift register or digital-to-analog converter (dac)]. the serial data output comes from each of the devices and are or -connected or sent to an or gate, to be received by the master. an or gate is only required if the connected devices do not support 3-state operation. the PGA280 provides a 3-state output if not active. pullup resistors may be required. as mentioned previously, the gpio pins are used to control an external multiplexer. in figure 57 , the three pins from gpio0, gpio1, and gpio2 are used as a mux address. two other gpio pins are used as ecs to enable communications with other slave devices. figure 57. example for connecting two additional spi devices selected by ecs copyright ? 2009, texas instruments incorporated submit documentation feedback 39 product folder link(s): PGA280 PGA280 gpio cs sclk mosi miso cs sclksdi sdo cs sclksdi sdo cs sclksdi sdo spi master addressingmux0 mux1 mux2 external mux a/d converter shift register or dac extended chip-select external mux control or
PGA280 sbos487a ? june 2009 ? revised september 2009 ................................................................................................................................................ www.ti.com checksum spi communication can be secured by adding a checksum byte to the write and read data. if this mode is activated by setting chksume (bit 0 in register 11), the PGA280 expects a valid checksum; otherwise, the device ignores the received data and sets chkerr in register 4. this event may require a register 4 read after each write completes. the PGA280 always responds to a read with checksum if sufficient sclk pulses (16) are provided after the command byte. a straight checksum (ignore carry) with a starting value of 0x9b, an 8-bit byte, is used. polynomial value: 1001 1010b = 0x9b ( b denotes binary, 0x denotes hex coding) write to device: command byte + data byte + chksum byte chksum = polynomial value + command byte + data byte * ; space read command to device = command byte + chksum byte response: data byte + chksum byte chksum = polynomial value + command byte + data byte * the command for activating the cs on a gpio pin (after configuration) is only a command byte: ? 11tx 0ccc ? . example: 0xc15c. this instruction activates cs on gpio1. the 5c is the checksum [(0x9b + 0xc1) mod 0x100 = 0x5c] the checksum is calculated only for the communication to or from the PGA280. in extended spi mode, if connecting the cs ( ecs) for other spi devices to the PGA280 port, the external device has to provide its own checksum character, if available. examples: 0x4101dd send reset [chksum calculation: (0x9b + 0x41 + 0x01) mod 0x100 = 0xdd] 0x4b11f7 activate chksum bit 0 of register 11. note that activation of the chk bit requires proper checksum. 0x8b260000 read configuration register 11 (contains 0x11) [0x9b + 0x8b = 0x26] 0x1137 response includes the chksum [0x9b + 0x8b + 0x11 = 0x37] 0x44ffdf reset all error flags in register 4 [0x9b + 0x44 + 0xff = 0xdf] 0x841f0000 read register 4 [0x9b + 0x84 = 0x1f] 0x001f no errors indicated if 00 [0x9b + 0x84 + 0x00 = 0x1f] commands can be chained while cs is active low; all bytes are added for checksum: examples: 0x4c 07 ee; activate mux0, mux1, and mux2 to gpio0, gpio1, and gpio2, respectively 0x64 ff fe 40 1b 59 80 d9 00 00; write to register 4 with buf trigger and reset all error flags : write to register 0 and set gain 1v/v; mux0 and mux1 set high : read register 0, provide 16 sclks 40 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): PGA280
package option addendum www.ti.com 11-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples PGA280aipw active tssop pw 24 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 PGA280a PGA280aipwr active tssop pw 24 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 PGA280a (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant PGA280aipwr tssop pw 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 q1 package materials information www.ti.com 11-apr-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) PGA280aipwr tssop pw 24 2000 367.0 367.0 38.0 package materials information www.ti.com 11-apr-2015 pack materials-page 2

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